Cypress Computer Hardware CY62148EV30 User Manual

MoBL® CY62148EV30  
4-Mbit (512K x 8) Static RAM  
Features  
Functional Description  
Very high speed: 45 ns  
The CY62148EV30 is a high performance CMOS static RAM  
organized as 512K words by 8 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL ) in portable  
Wide voltage range: 2.20V to 3.60V  
®
Temperature ranges  
Industrial: –40°C to +85°C  
Automotive-A: –40°C to +85°C  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption. Placing the device into standby mode reduces  
power consumption by more than 99 percent when deselected  
(CE HIGH). The eight input and output pins (IO through IO ) are  
Pin compatible with CY62148DV30  
Ultra low standby power  
0
7
placed in a high impedance state when the device is deselected  
(CE HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW and WE LOW).  
Typical standby current: 1 μA  
Maximum standby current: 7 μA (Industrial)  
Ultra low active power  
Typical active current: 2 mA at f = 1 MHz  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. Data on the eight IO pins (IO through IO ) is  
0
7
then written into the location specified on the address pins (A  
Easy memory expansion with CE, and OE features  
Automatic power down when deselected  
0
through A ).  
18  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under  
these conditions, the contents of the memory location specified  
by the address pins appear on the IO pins.  
CMOS for optimum speed and power  
Available in Pb-free 36-ball VFBGA, 32-pin TSOP II and 32-pin  
[1]  
SOIC packages  
Logic Block Diagram  
A
0
IO  
0
INPUT BUFFER  
A
1
A
2
IO  
1
A
3
A
4
IO  
2
A
5
A
6
512K x 8  
ARRAY  
IO  
3
A
A
A
A
A
A
7
8
IO  
4
9
10  
11  
12  
IO  
5
IO  
6
CE  
IO  
POWER  
DOWN  
7
COLUMN DECODER  
WE  
OE  
Notes  
1. SOIC package is available only in 55 ns speed bin.  
2. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05576 Rev. *G  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 4, 2008  
 
   
MoBL® CY62148EV30  
DC Input Voltage  
.....................–0.3V to V  
+ 0.3V  
Maximum Ratings  
CC(max)  
Output Current into Outputs (LOW)............................. 20 mA  
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Static Discharge Voltage.......................................... > 2001V  
(MIL-STD-883, Method 3015)  
Storage Temperature.................................. –65°C to +150°C  
Latch up Current.....................................................> 200 mA  
Ambient Temperature with  
Power Applied .............................................. 55°C to +125°C  
Operating Range  
Supply Voltage to Ground  
Potential..........................................–0.3V to V  
Ambient  
Product  
Range  
V
CC  
+ 0.3V  
+ 0.3V  
CC(max)  
Temperature  
DC Voltage Applied to Outputs  
CY62148EV30 Ind’l/Auto-A –40°C to +85°C 2.2V to 3.6V  
in High-Z State  
........................–0.3V to V  
CC(max)  
Electrical Characteristics (Over the Operating Range)  
- 45 (Ind’l/Auto-A)  
- 55  
Parameter  
Description  
Test Conditions  
= –0.1 mA  
Unit  
Min Typ  
2.0  
Max  
Min Typ  
Max  
V
V
V
V
Output HIGH  
Voltage  
I
I
I
I
2.0  
2.4  
V
V
V
V
V
V
V
OH  
OL  
IH  
OH  
OH  
OL  
OL  
= –1.0 mA, V > 2.70V  
2.4  
CC  
Output LOW  
Voltage  
= 0.1 mA  
0.4  
0.4  
0.2  
0.4  
= 2.1 mA, V > 2.70V  
CC  
Input HIGH  
Voltage  
V
V
V
= 2.2V to 2.7V  
= 2.7V to 3.6V  
1.8  
2.2  
V
V
+ 0.3V 1.8  
+ 0.3V 2.2  
V
V
+ 0.3V  
CC  
CC  
CC  
CC  
CC  
CC  
CC  
+ 0.3V  
Input LOW  
Voltage  
= 2.2V to 2.7V For VFBGA and  
TSOP II package  
–0.3  
0.6  
IL  
For SOIC package  
–0.3  
0.4  
V
V
V
= 2.7V to 3.6V For VFBGA and  
TSOP II package  
–0.3  
0.8  
CC  
For SOIC package  
–0.3  
–1  
0.6  
+1  
I
Input Leakage  
Current  
GND < V < V  
CC  
–1  
–1  
+1  
+1  
μA  
μA  
IX  
I
I
Output Leakage GND < V < V , Output Disabled  
–1  
+1  
20  
OZ  
O
CC  
Current  
I
V
Operating  
f = f  
= 1/t  
V
= V  
CC(max),  
15  
2
20  
15  
2
mA  
CC  
CC  
max  
RC  
CC  
Supply Current  
I
= 0 mA,  
OUT  
f = 1 MHz  
CE > V – 0.2V,  
2.5  
2.5  
7
CMOS levels  
I
Automatic CE  
Power Down  
CurrentCMOS f = f  
1
7
7
1
μA  
μA  
SB1  
CC  
CC  
V
> V – 0.2V, V < 0.2V  
IN  
IN  
(Address and Data Only),  
max  
Inputs  
f = 0 (OE and WE), V = 3.60V  
CC  
I
Automatic CE  
Power Down  
CE > V – 0.2V,  
1
1
7
SB2  
CC  
V
> V – 0.2V or V < 0.2V,  
IN  
CC IN  
CurrentCMOS f = 0, V = 3.60V  
CC  
Inputs  
Notes  
5.  
6.  
V
V
= –2.0V for pulse durations less than 20 ns.  
IL(min)  
= V + 0.75V for pulse durations less than 20 ns.  
IH(max)  
CC  
7. Full device AC operation assumes a minimum of 100 μs ramp time from 0 to V  
and 200 μs wait time after V stabilization.  
CC  
CC(min)  
8. Under DC conditions the device meets a V of 0.8V (for V range of 2.7V to 3.6V) and 0.6V (for V range of 2.2V to 2.7V). However, in dynamic conditions  
IL  
CC  
CC  
Input LOW voltage applied to the device must not be higher than 0.6V and 0.4V for the above ranges. This is applicable to SOIC package only. Please refer to  
AN13470 for details.  
9. Only chip enable (CE) must be HIGH at CMOS level to meet the I  
/ I  
spec. Other inputs can be left floating.  
SB2 CCDR  
Document #: 38-05576 Rev. *G  
Page 3 of 12  
 
         
MoBL® CY62148EV30  
Capacitance (For All packages)  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max  
10  
Unit  
pF  
C
IN  
A
V
= V  
CC  
CC(typ)  
C
10  
pF  
OUT  
Thermal Resistance [10]  
VFBGA  
TSOP II  
SOIC  
Parameter  
Description  
Test Conditions  
Unit  
Package Package Package  
Θ
Thermal Resistance  
(Junction to Ambient)  
Still Air, soldered on a 3 x 4.5 inch,  
two-layer printed circuit board  
72  
75.13  
8.95  
55  
22  
°C/W  
°C/W  
JA  
Θ
Thermal Resistance  
(Junction to Case)  
8.86  
JC  
AC Test Loads and Waveforms  
R1  
ALL INPUT PULSES  
90%  
V
CC  
V
OUTPUT  
CC  
90%  
10%  
10%  
R2  
GND  
Rise Time = 1 V/ns  
30 pF  
Fall Time = 1 V/ns  
INCLUDING  
JIG AND  
SCOPE  
Equivalent to:  
THEVENIN EQUIVALENT  
R
TH  
OUTPUT  
V
Parameters  
2.50V  
16667  
15385  
8000  
3.0V  
1103  
1554  
645  
Unit  
Ω
R1  
R2  
Ω
R
Ω
TH  
V
1.20  
1.75  
V
TH  
Data Retention Characteristics (Over the Operating Range)  
Parameter  
Description  
Conditions  
Min  
Typ  
Max Unit  
V
V
for Data Retention  
1.5  
V
DR  
CC  
I
Data Retention Current  
V
V
=1.5V, CE> V 0.2V, Ind’l/Auto-A  
0.8  
7
μA  
CCDR  
CC  
CC  
> V – 0.2V or V  
<
IN  
CC  
IN  
0.2V  
t
t
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
ns  
ns  
CDR  
t
R
RC  
Data Retention Waveform  
DATA RETENTION MODE  
> 1.5V  
V
V
CC(min)  
V
CC(min)  
VCC  
DR  
t
t
R
CDR  
CE  
Notes  
10. Tested initially and after any design or process changes that may affect these parameters.  
11. Full device AC operation requires linear V ramp from V to V > 100 μs or stable at V > 100 μs.  
CC(min)  
CC  
DR  
CC(min)  
Document #: 38-05576 Rev. *G  
Page 4 of 12  
 
     
MoBL® CY62148EV30  
Switching Characteristics  
(Over the Operating Range)  
- 45 (Ind’l/Auto-A)  
- 55  
Parameter  
Read Cycle  
Description  
Unit  
Min  
Max  
Min  
Max  
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
45  
55  
10  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
Data Hold from Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
45  
55  
AA  
10  
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
PU  
45  
22  
55  
25  
OE LOW to Low Z  
5
10  
0
5
10  
0
OE HIGH to High Z  
18  
18  
45  
20  
20  
55  
CE LOW to Low Z  
CE HIGH to High Z  
CE LOW to Power Up  
CE HIGH to Power Up  
PD  
Write Cycle  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
45  
35  
35  
0
55  
40  
40  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE LOW to Write End  
Address Setup to Write End  
Address Hold from Write End  
Address Setup to Write Start  
WE Pulse Width  
SCE  
AW  
HA  
0
0
SA  
35  
25  
0
40  
25  
0
PWE  
SD  
Data Setup to Write End  
Data Hold from Write End  
HD  
WE LOW to High Z  
18  
20  
HZWE  
LZWE  
WE HIGH to Low Z  
10  
10  
Notes  
12. Test Conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less (1 V/ns), timing reference levels of V  
/2, input  
CC(typ)  
pulse levels of 0 to V  
, and output loading of the specified I /I as shown in the “AC Test Loads and Waveforms” on page 4.  
CC(typ)  
OL OH  
13. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
for any given device.  
LZWE  
HZCE  
LZCE HZOE  
LZOE  
HZWE  
14. t  
, t  
, and t  
transitions are measured when the output enter a high impedance state.  
HZOE HZCE  
HZWE  
15. The internal write time of the memory is defined by the overlap of WE, CE = V . All signals must be ACTIVE to initiate a write and any of these signals can  
IL  
terminate a write by going INACTIVE. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.  
Document #: 38-05576 Rev. *G  
Page 5 of 12  
 
       
MoBL® CY62148EV30  
Switching Waveforms  
Figure 1. Read Cycle No. 1 (Address Transition Controlled)  
tRC  
ADDRESS  
DATA OUT  
t
AA  
t
OHA  
PREVIOUS DATA VALID  
DATA VALID  
Figure 2. Read Cycle No. 2 (OE Controlled)  
ADDRESS  
CE  
t
RC  
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCE  
t
PD  
ICC  
t
V
CC  
PU  
50%  
SUPPLY  
CURRENT  
50%  
ISB  
Figure 3. Write Cycle No. 1 (WE Controlled, OE HIGH During Write)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
OE  
t
t
SD  
HD  
DATA IO  
NOTE  
DATA VALID  
t
HZOE  
Notes  
16. Device is continuously selected. OE, CE = V .  
IL  
17. WE is HIGH for read cycles.  
18. Address valid before or similar to CE transition LOW.  
19. Data IO is high impedance if OE = V  
.
IH  
20. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.  
21. During this period, the IOs are in output state. Do not apply input signals.  
Document #: 38-05576 Rev. *G  
Page 6 of 12  
 
           
MoBL® CY62148EV30  
Switching Waveforms (continued)  
Figure 4. Write Cycle No. 2 (CE Controlled)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
t
AW  
HA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IO  
DATA VALID  
Figure 5. Write Cycle No. 3 (WE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
NOTE  
DATA VALID  
DATA IO  
t
t
LZWE  
HZWE  
Truth Table  
CE  
H
L
WE  
X
OE  
Inputs/Outputs  
Mode  
Power  
Standby (I  
X
L
High Z  
Deselect/Power down  
Read  
)
SB  
H
Data Out  
High Z  
Active (I  
Active (I  
Active (I  
)
CC  
L
H
H
X
Output Disabled  
Write  
)
CC  
L
L
Data in  
)
CC  
Document #: 38-05576 Rev. *G  
Page 7 of 12  
 
MoBL® CY62148EV30  
Ordering Information  
Speed  
(ns)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
45  
CY62148EV30LL-45BVXI 51-85149 36-ball Very Fine Pitch Ball Grid Array (Pb-free)  
CY62148EV30LL-45ZSXI 51-85095 32-pin Thin Small Outline Package II (Pb-free)  
CY62148EV30LL-45ZSXA 51-85095 32-pin Thin Small Outline Package II (Pb-free)  
Industrial  
Automotive-A  
Industrial  
55  
CY62148EV30LL-55SXI  
51-85081 32-pin Small Outline Integrated Circuit (Pb-free)  
Contact your local Cypress sales representative for availability of these parts.  
Package Diagrams  
Figure 6. 36-ball VFBGA (6 x 8 x 1 mm) (51-85149)  
BOTTOM VIEW  
A1 CORNER  
TOP VIEW  
Ø0.05 M C  
Ø0.25 M C A B  
A1 CORNER  
Ø0.30 0.05(36X)  
1
2
3
4
5
6
6
5
4
3
2
1
A
A
B
C
D
B
C
D
E
E
F
F
G
G
H
H
1.875  
A
A
0.75  
B
6.00 0.10  
3.75  
B
6.00 0.10  
0.15(4X)  
SEATING PLANE  
C
51-85149-*C  
Document #: 38-05576 Rev. *G  
Page 8 of 12  
 
MoBL® CY62148EV30  
Package Diagrams (continued)  
Figure 7. 32-pin TSOP II (51-85095)  
51-85095-**  
Document #: 38-05576 Rev. *G  
Page 9 of 12  
 
MoBL® CY62148EV30  
Package Diagrams (continued)  
Figure 8. 32-pin (450 MIL) Molded SOIC (51-85081)  
16  
1
0.546[13.868]  
0.566[14.376]  
0.440[11.176]  
0.450[11.430]  
17  
32  
0.793[20.142]  
0.817[20.751]  
0.006[0.152]  
0.012[0.304]  
0.101[2.565]  
0.111[2.819]  
0.118[2.997]  
MAX.  
0.004[0.102]  
0.047[1.193]  
0.063[1.600]  
0.004[0.102]  
0.050[1.270]  
BSC.  
0.023[0.584]  
0.039[0.990]  
MIN.  
0.014[0.355]  
0.020[0.508]  
SEATING PLANE  
51-85081-*B  
Document #: 38-05576 Rev. *G  
Page 10 of 12  
 
MoBL® CY62148EV30  
Document History Page  
®
Document Title: CY62148EV30 MoBL 4-Mbit (512K x 8) Static RAM  
Document Number: 38-05576  
Revision  
ECN  
Submission Orig. of  
Description of Change  
Date  
Change  
**  
223225  
247373  
See ECN  
See ECN  
AJU  
New data sheet  
*A  
SYT Changed from Advance Information to Preliminary  
Moved Product Portfolio to Page 2  
Changed V stabilization time in footnote #7 from 100 μs to 200 μs  
CC  
Changed I  
from 2.0 μA to 2.5 μA  
CCDR  
Changed typo in Data Retention Characteristics (t ) from 100 μs to t ns  
R
RC  
Changed t  
Changed t  
from 6 ns to 10 ns for both 35 ns and 45 ns Speed Bin  
OHA  
, t  
from 12 to 15 ns for 35 ns Speed Bin and 15 to 18 ns for  
HZOE HZWE  
45 ns Speed Bin  
Changed t  
Speed Bin  
Changed t  
Speed Bin  
from 25 to 30 ns for 35 ns Speed Bin and 40 to 35 ns for 45 ns  
SCE  
from 12 to 18 ns for 35 ns Speed Bin and 15 to 22 ns for 45 ns  
HZCE  
Changed t from 15 to 18 ns for 35 ns Speed Bin and 20 to 22 ns for  
SD  
45 ns Speed Bin  
Changed t  
from 15 to 18 ns for 35 ns Speed Bin  
DOE  
Changed Ordering Information to include Pb-Free Packages  
*B  
414807  
See ECN  
ZSD Changed from Preliminary information to Final  
Changed the address of Cypress Semiconductor Corporation on Page #1 from  
“3901 North First Street” to “198 Champion Court”  
Removed 35ns Speed Bin  
Removed “L” version of CY62148EV30  
Changed ball C3 from DNU to NC.  
Removed the redundant footnote on DNU.  
Changed I (max) value from 2 mA to 2.5 mA and I (Typ) value from  
CC  
CC  
1.5 mA to 2 mA at f=1 MHz  
Changed I (Typ) value from 12 mA to 15 mA at f = f  
CC  
max  
Changed I  
and I  
Typ values from 0.7 μA to 1 μA and Max values from 2.5  
SB1  
SB2  
μA to 7 μA.  
Changed the AC test load capacitance value from 50pF to 30pF.  
Changed I from 2.5 μA to 7 μA.  
CCDR  
Added I  
typical value.  
CCDR  
Changed t  
Changed t  
Changed t  
Changed t  
from 3 ns to 5 ns  
LZOE  
LZCE  
HZCE  
PWE  
and t  
from 6 ns to 10 ns  
LZWE  
from 22 ns to 18 ns  
from 30 ns to 35 ns.  
Changed t from 22 ns to 25 ns.  
SD  
Updated the package diagram 36-pin VFBGA from *B to *C  
Added 32-pin SOIC package diagram and pin diagram  
Updated the ordering information table and replaced the Package Name column  
with Package Diagram.  
*C  
464503  
See ECN  
NXR Included Automotive Range in product offering  
Updated Thermal Resistance table  
Updated the Ordering Information  
*D  
*E  
833080  
890962  
See ECN  
See ECN  
VKN Added footnote 8  
Added V spec for SOIC package  
IL  
VKN Removed Automotive part and its related information  
Added footnote 2 related to SOIC package  
Added footnote 9 related to I  
SB2  
Added AC values for 55 ns Industrial-SOIC range  
Updated Ordering Information table  
Document #: 38-05576 Rev. *G  
Page 11 of 12  
 
MoBL® CY62148EV30  
®
Document Title: CY62148EV30 MoBL 4-Mbit (512K x 8) Static RAM  
Document Number: 38-05576  
Revision  
ECN  
Submission Orig. of  
Description of Change  
Date  
Change  
*F  
987940  
See ECN  
VKN Changed V spec from 0.4V to 0.2V for SOIC package at I = 0.1 mA  
OL  
OL  
Changed V spec from 0.6V to 0.4V for SOIC package at V = 2.2V to 2.7V  
IL  
CC  
Updated footnote 8  
Made footnote 9 applicable for both I  
and I  
CCDR  
SB2  
*G  
2548575  
08/05/08  
NXR Added Auto-A information.  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
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© Cypress Semiconductor Corporation, 2004-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 38-05576 Rev. *G  
Revised August 4, 2008  
Page 12 of 12  
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor. All product and company names mentioned in this document are the  
trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders.  
 

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