Cypress Computer Hardware CY62256 User Manual

CY62256  
256K (32K x 8) Static RAM  
Features  
Functional Description[1]  
• High speed: 55 ns and 70 ns  
The CY62256 is a high-performance CMOS static RAM  
organized as 32K words by 8 bits. Easy memory expansion is  
provided by an active LOW chip enable (CE) and active LOW  
output enable (OE) and three-state drivers. This device has an  
automatic power-down feature, reducing the power  
consumption by 99.9% when deselected.  
• Voltage range: 4.5V–5.5V operation  
• Low active power (70 ns, LL version)  
— 275 mW (max.)  
• Low standby power (70 ns, LL version)  
28 µW (max.)  
An active LOW write enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
Easy memory expansion with CE and OE features  
TTL-compatible inputs and outputs  
Automatic power-down when deselected  
CMOS for optimum speed/power  
(I/O through I/O ) is written into the memory location  
0
7
addressed by the address present on the address pins (A  
0
through A ). Reading the device is accomplished by selecting  
14  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins are present on the eight data input/output pins.  
Package available in a standard 450-mil-wide (300-mil  
body width) 28-lead narrow SOIC, 28-lead TSOP-1,  
28-lead reverse TSOP-1, and 600-mil 28-lead PDIP  
packages  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH.  
Logic Block Diagram  
I/O  
0
1
2
INPUTBUFFER  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
A
10  
A
9
A
8
A
7
A
3
4
5
6
A
512 x 512  
ARRAY  
5
A
4
3
A
A
2
CE  
WE  
6
7
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
OE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note System Design Guidelineson http://www.cypress.com.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05248 Rev. *B  
Revised August 27, 2002  
 
CY62256  
Electrical Characteristics Over the Operating Range (continued)  
CY6225655  
CY6225670  
[3]  
[3]  
Parameter  
Description  
Automatic CE  
Power-down Current—  
Test Conditions  
Max. V , CE > V 0.3V  
Min. Typ.  
Max. Min. Typ.  
Max. Unit  
I
1
5
50  
5
1
2
5
50  
5
mA  
µA  
µA  
µA  
SB2  
CC  
CC  
V
> V 0.3V, or V  
<
IN  
CC  
IN  
L
2
CMOS Inputs  
0.3V, f = 0  
LL  
LL  
0.1  
0.1  
0.1  
0.1  
Industl Temp Range  
10  
10  
Capacitance[4]  
Parameter  
Description  
Test Conditions  
Max.  
Unit  
pF  
C
C
Input Capacitance  
Output Capacitance  
T = 25°C, f = 1 MHz,  
6
8
IN  
A
V
= 5.0V  
CC  
pF  
OUT  
AC Test Loads and Waveforms  
R1 1800  
R1 1800Ω  
5V  
5V  
OUTPUT  
ALL INPUT PULSES  
90%  
OUTPUT  
3.0V  
GND  
90%  
10%  
10%  
R2  
990Ω  
R2  
990Ω  
100 pF  
5 pF  
< 5 ns  
< 5 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(a)  
(b)  
Equivalent to:  
THÉVENIN EQUIVALENT  
639Ω  
OUTPUT  
1.77V  
Data Retention Characteristics  
[5]  
[3]  
Parameter  
Description  
for Data Retention  
CC  
Conditions  
Min.  
Typ.  
Max.  
Unit  
V
V
V
2.0  
DR  
I
Data Retention Current  
L
V
= 3.0V, CE > V 0.3V,  
> V 0.3V, or V < 0.3V  
CC IN  
2
50  
5
µA  
µA  
µA  
ns  
CCDR  
CC  
CC  
V
IN  
LL  
0.1  
0.1  
LL Indl  
10  
[4]  
t
t
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
CDR  
[4]  
t
ns  
R
RC  
Data Retention Waveform  
DATA RETENTION MODE  
> 2V  
3.0V  
3.0V  
V
V
CC  
DR  
t
t
R
CDR  
CE  
Notes:  
4. Tested initially and after any design or process changes that may affect these parameters.  
5. No input may exceed VCC + 0.5V.  
Document #: 38-05248 Rev. *B  
Page 3 of 11  
 
CY62256  
[6]  
Switching Characteristics Over the Operating Range  
CY6225655  
CY6225670  
Parameter  
Description  
Min.  
Max.  
Min.  
70  
5
Max.  
Unit  
Read Cycle  
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
55  
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
55  
70  
AA  
Data Hold from Address Change  
CE LOW to Data Valid  
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
PU  
55  
25  
70  
35  
OE LOW to Data Valid  
[7]  
OE LOW to Low-Z  
5
5
0
5
5
0
[7, 8]  
OE HIGH to High-Z  
20  
20  
55  
25  
25  
70  
[7]  
CE LOW to Low-Z  
[7, 8]  
CE HIGH to High-Z  
CE LOW to Power-up  
CE HIGH to Power-down  
PD  
[9, 10]  
Write Cycle  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
55  
45  
45  
0
70  
60  
60  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE LOW to Write End  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
WE Pulse Width  
SCE  
AW  
HA  
0
0
SA  
40  
25  
0
50  
30  
0
PWE  
SD  
Data Set-up to Write End  
Data Hold from Write End  
HD  
[7, 8]  
WE LOW to High-Z  
20  
25  
HZWE  
LZWE  
[7]  
WE HIGH to Low-Z  
5
5
Switching Waveforms  
[11, 12]  
Read Cycle No. 1  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Notes:  
6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
OL/IOH and 100-pF load capacitance.  
I
7. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.  
8. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.  
9. The internal Write time of the memory is defined by the overlap of CELOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate  
a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write.  
10. The minimum Write cycle time for Write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD  
11. Device is continuously selected. OE, CE = VIL.  
12. WE is HIGH for Read cycle.  
Document #: 38-05248 Rev. *B  
Page 4 of 11  
 
CY62256  
Switching Waveforms (continued)  
[12, 13]  
Read Cycle No. 2  
t
RC  
CE  
t
ACE  
OE  
t
t
HZOE  
t
DOE  
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PD  
t
PU  
V
ICC  
ISB  
CC  
SUPPLY  
CURRENT  
50%  
50%  
[9, 14, 15]  
Write Cycle No. 1 (WE Controlled)  
t
WC  
ADDRESS  
CE  
t
t
AW  
HA  
t
SA  
t
PWE  
WE  
OE  
t
SD  
t
HD  
DATA VALID  
IN  
DATA I/O  
16  
NOTE  
t
HZOE  
[9, 14, 15]  
Write Cycle No. 2 (CE Controlled)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
t
HA  
AW  
WE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
IN  
Notes:  
13. Address valid prior to or coincident with CE transition LOW.  
14. Data I/O is high impedance if OE = VIH  
.
15. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
Document #: 38-05248 Rev. *B  
Page 5 of 11  
 
CY62256  
Switching Waveforms (continued)  
[10, 15]  
Write Cycle No. 3 (WE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
t
HA  
AW  
t
SA  
WE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
NOTE 16  
IN  
t
t
LZWE  
HZWE  
Note:  
16. During this period, the I/Os are in output state and input signals should not be applied.  
Document #: 38-05248 Rev. *B  
Page 6 of 11  
 
CY62256  
Typical DC and AC Characteristics  
CURRENT  
STANDBY  
vs. AMBIENT TEMPERATURE  
NORMALIZED SUPPLY CURRENT  
vs. AMBIENT TEMPERATURE  
NORMALIZED SUPPLY CURRENT  
vs. SUPPLY VOLTAGE  
1.4  
3.0  
2.5  
2.0  
1.5  
1.0  
1.4  
I
CC  
1.2  
1.0  
0.8  
0.6  
1.2  
1.0  
0.8  
0.6  
I
CC  
I
SB  
V
IN  
=5.0V  
T =25°C  
A
V
V
IN  
=5.0V  
=5.0V  
0.5  
0.4  
CC  
0.4  
V
V
IN  
=5.0V  
=5.0V  
CC  
0.2  
0.0  
0.0  
0.2  
0.0  
55  
I
SB  
-0.5  
55  
25  
105  
25  
125  
4.0  
4.5  
5.0  
5.5  
6.0  
AMBIENT TEMPERATURE (°C)  
AMBIENT TEMPERATURE (°C)  
SUPPLY VOLTAGE (V)  
NORMALIZED ACCESS TIME  
vs. AMBIENT TEMPERATURE  
OUTPUT SINK CURRENT  
vs. OUTPUT VOLTAGE  
NORMALIZED ACCESS TIME  
vs. SUPPLY VOLTAGE  
140  
120  
1.6  
1.4  
1.4  
1.3  
1.2  
100  
80  
1.2  
1.0  
1.1  
1.0  
60  
T =25°C  
A
V
CC  
=5.0V  
T =25°C  
A
V
CC  
=5.0V  
40  
0.8  
20  
0
0.9  
0.8  
0.6  
55  
0.0  
1.0  
2.0  
3.0  
4.0  
25  
125  
4.0  
4.5  
5.0  
5.5  
6.0  
AMBIENT TEMPERATURE (°C)  
OUTPUT VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
OUTPUT SOURCE CURRENT  
vs. OUTPUT VOLTAGE  
120  
100  
80  
V
=5.0V  
CC  
60  
T =25°C  
A
40  
20  
0
0.0  
1.0  
2.0  
3.0  
4.0  
OUTPUT VOLTAGE (V)  
Document #: 38-05248 Rev. *B  
Page 7 of 11  
 
CY62256  
Typical DC and AC Characteristics (continued)  
TYPICAL POWER-ON CURRENT  
vs. SUPPLY VOLTAGE  
TYPICAL ACCESS TIME CHANGE  
vs. OUTPUT LOADING  
NORMALIZED I vs.CYCLETIME  
CC  
3.0  
2.5  
2.0  
1.5  
30.0  
25.0  
20.0  
15.0  
1.25  
1.00  
0.75  
0.50  
V
=5.0V  
CC  
T =25°C  
A
V
IN  
=0.5V  
V
=4.5V  
1.0  
0.5  
10.0  
5.0  
CC  
T =25°C  
A
0.0  
0.0  
0.0  
1.0  
2.0  
3.0  
4.0  
5.0  
0
200 400  
600 800 1000  
10  
20  
30  
40  
SUPPLY VOLTAGE (V)  
CAPACITANCE (pF)  
CYCLE FREQUENCY (MHz)  
Truth Table  
CE  
H
L
WE  
X
OE  
X
Inputs/Outputs  
High-Z  
Mode  
Power  
Deselect/Power-down  
Read  
Standby (I  
)
SB  
H
L
Data Out  
Data In  
High-Z  
Active (I  
Active (I  
Active (I  
)
CC  
L
L
X
Write  
)
CC  
L
H
H
Deselect, Output Disabled  
)
CC  
Ordering Information  
Speed  
Package  
Name  
Operating  
Range  
(ns)  
Ordering Code  
CY62256LL55SNI  
Package Type  
55  
SN28  
Z28  
28-lead (300-Mil Narrow Body) Narrow SOIC  
28-lead Thin Small Outline Package  
Industrial  
CY62256LL55ZI  
CY6225670SNC  
CY62256L70SNC  
CY62256LL70SNC  
CY62256L70SNI  
CY62256LL70SNI  
CY62256LL70ZC  
CY62256LL70ZI  
CY6225670PC  
70  
SN28  
28-lead (300-Mil Narrow Body) Narrow SOIC  
Commercial  
Industrial  
Z28  
Z28  
28-lead Thin Small Outline Package  
28-lead (600-Mil) Molded DIP  
Commercial  
Industrial  
P15  
P15  
P15  
ZR28  
Commercial  
CY62256L70PC  
CY62256LL70PC  
CY62256LL70ZRI  
28-lead Reverse Thin Small Outline Package  
Industrial  
Document #: 38-05248 Rev. *B  
Page 8 of 11  
 
CY62256  
Package Diagrams  
28-lead (600-mil) Molded DIP P15  
51-85017-A  
28-lead (300-mil) SNC (Narrow Body) SN28  
51-85092-*B  
Document #: 38-05248 Rev. *B  
Page 9 of 11  
 
CY62256  
Package Diagrams (continued)  
28-lead Thin Small Outline Package Type 1 (8 x 13.4 mm) Z28  
51-85071-*G  
28-lead Reverse Type 1 Thin Small Outline Package (8 x 13.4 mm) ZR28  
51-85074-*F  
All product and company names mentioned in this document are the trademarks of their respective holders.  
Document #: 38-05248 Rev. *B  
Page 10 of 11  
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.  
 
CY62256  
Document Title: CY62256 256K (32K x 8) Static RAM  
Document Number: 38-05248  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
113454  
03/06/02  
MGN  
Change from Spec number: 38-00455 to 38-05248  
Remove obsolete parts from ordering info, standardize format  
*A  
*B  
115227  
116506  
05/23/02  
09/04/02  
GBI  
GBI  
Changed SN Package Diagram  
Added footnote 1.  
Corrected package description in Ordering Information table  
Document #: 38-05248 Rev. *B  
Page 11 of 11  
 

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