Cypress Computer Hardware CY7C1006D User Manual

CY7C106D  
CY7C1006D  
1-Mbit (256K x 4) Static RAM  
Features  
Functional Description [1]  
• Pin- and function-compatible with CY7C106B/CY7C1006B  
• High speed  
The CY7C106D and CY7C1006D are high-performance  
CMOS static RAMs organized as 262,144 words by 4 bits.  
Easy memory expansion is provided by an active LOW Chip  
Enable (CE), an active LOW Output Enable (OE), and tri-state  
drivers. These devices have an automatic power-down feature  
that reduces power consumption by more than 65% when the  
— t = 10 ns  
AA  
• Low active power  
— I = 80 mA @ 10 ns  
CC  
devices are deselected. The four input and output pins (IO  
0
• Low CMOS standby power  
through IO ) are placed in a high-impedance state when:  
3
— I  
= 3.0 mA  
SB2  
• Deselected (CE HIGH)  
• 2.0V Data Retention  
• Outputs are disabled (OE HIGH)  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• TTL-compatible inputs and outputs  
• When the write operation is active (CE and WE LOW)  
Write to the device by taking Chip Enable (CE) and Write  
Enable (WE) inputs LOW. Data on the four IO pins (IO  
0
• CY7C106DavailableinPb-free28-pin400-MilwideMolded  
SOJ package. CY7C1006D available in Pb-free 28-pin  
300-Mil wide Molded SOJ package  
through IO ) is then written into the location specified on the  
3
address pins (A through A ).  
0
17  
Read from the device by taking Chip Enable (CE) and Output  
Enable (OE) LOW while forcing Write Enable (WE) HIGH.  
Under these conditions, the contents of the memory location  
specified by the address pins appears on the four IO pins.  
Logic Block Diagram  
INPUT BUFFER  
A
1
A
2
IO  
0
A
3
256K x 4  
ARRAY  
A
A
A
A
A
A
IO  
1
4
5
6
7
8
9
IO  
2
IO  
3
CE  
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Note  
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05459 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 22, 2007  
 
 
CY7C106D  
CY7C1006D  
DC Input Voltage ............................... –0.5V to V + 0.5V  
Maximum Ratings  
CC  
Current into Outputs (LOW) ........................................ 20 mA  
Exceeding the maximum ratings may impair the useful life of  
the device. These user guidelines are not tested.  
Static Discharge Voltage .......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
Storage Temperature .................................65°C to +150°C  
Latch-up Current .................................................... > 200 mA  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
Operating Range  
Supply Voltage on V Relative to GND ... –0.5V to +6.0V  
CC  
Ambient  
Range  
V
Speed  
DC Voltage Applied to Outputs  
in High-Z State ...................................–0.5V to V + 0.5V  
CC  
Temperature  
CC  
Industrial  
–40°C to +85°C  
5V ± 0.5V  
10 ns  
Electrical Characteristics (Over the Operating Range)  
7C106D-10  
7C1006D-10  
Parameter  
Description  
Test Conditions  
Unit  
Min  
2.4  
Max  
V
Output HIGH Voltage  
Output LOW Voltage  
Input HIGH Voltage  
I
I
= –4.0 mA  
V
V
OH  
OL  
IH  
OH  
OL  
V
V
V
I
= 8.0 mA  
0.4  
2.2  
–0.5  
–1  
V
+ 0.5  
V
CC  
Input LOW Voltage  
0.8  
+1  
+1  
80  
72  
58  
37  
10  
V
IL  
Input Leakage Current  
Output Leakage Current  
GND < V < V  
CC  
µA  
µA  
mA  
mA  
mA  
mA  
mA  
IX  
I
I
I
GND < V < V , Output Disabled  
–1  
OZ  
I
CC  
V
Operating Supply Current  
V
I
f = f  
= Max,  
100 MHz  
83 MHz  
66 MHz  
40 MHz  
CC  
CC  
CC  
= 0 mA,  
OUT  
= 1/t  
max  
RC  
I
I
Automatic CE Power-Down  
Current—TTL Inputs  
Max V , CE > V ,  
CC IH  
V
SB1  
SB2  
> V or V < V , f = f  
IN  
IH IN IL max  
Automatic CE Power-Down  
Current—CMOS Inputs  
Max V , CE > V – 0.3V,  
V
3
mA  
CC  
CC  
> V – 0.3V or V < 0.3V, f=0  
IN  
CC  
IN  
Note  
3.  
V
(min) = –2.0V and V (max) = V + 1V for pulse durations of less than 5 ns.  
IH CC  
IL  
Document #: 38-05459 Rev. *E  
Page 3 of 11  
 
 
CY7C106D  
CY7C1006D  
Capacitance [4]  
Parameter  
Description  
Test Conditions  
Max  
7
Unit  
pF  
C : Addresses Input Capacitance  
T = 25°C, f = 1 MHz, V = 5.0V  
IN  
A
CC  
C : Controls  
10  
10  
pF  
IN  
C
Output Capacitance  
pF  
OUT  
Thermal Resistance [4]  
300-Mil  
400-Mil  
Unit  
Parameter  
Description  
Test Conditions  
Wide SOJ Wide SOJ  
Θ
Θ
Thermal Resistance  
(Junction to Ambient)  
Still Air, soldered on a 3 × 4.5 inch,  
four-layer printed circuit board  
59.16  
40.84  
58.76  
°C/W  
°C/W  
JA  
Thermal Resistance  
(Junction to Case)  
40.54  
JC  
AC Test Loads and Waveforms [5]  
ALL INPUT PULSES  
3.0V  
Z = 50Ω  
90%  
10%  
90%  
10%  
OUTPUT  
50Ω  
GND  
30 pF*  
* CAPACITIVE LOAD CONSISTS  
OF ALL COMPONENTS OF THE  
TEST ENVIRONMENT  
1.5V  
Fall Time: 3 ns  
Rise Time: 3 ns  
(b)  
(a)  
High-Z characteristics:  
R1 480Ω  
5V  
OUTPUT  
R2  
255Ω  
5 pF  
INCLUDING  
JIG AND  
SCOPE  
(c)  
Notes  
4. Tested initially and after any design or process changes that may affect these parameters.  
5. AC characteristics (except High-Z) are tested using the load conditions shown in Figure (a). High-Z characteristics are tested for all speeds using the test load  
shown in Figure (c).  
Document #: 38-05459 Rev. *E  
Page 4 of 11  
 
     
CY7C106D  
CY7C1006D  
[6]  
Switching Characteristics (Over the Operating Range)  
7C106D-10  
7C1006D-10  
Parameter  
Description  
Unit  
Min  
Max  
Read Cycle  
[7]  
t
V
(typical) to the first access  
100  
10  
µs  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
power  
CC  
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
RC  
Address to Data Valid  
Data Hold from Address Change  
CE LOW to Data Valid  
OE LOW to Data Valid  
OE LOW to Low Z  
10  
AA  
3
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
10  
5
0
3
0
OE HIGH to High Z  
5
5
CE LOW to Low Z  
CE HIGH to High Z  
CE LOW to Power-Up  
PU  
PD  
CE HIGH to Power-Down  
10  
Write Cycle  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
10  
7
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE LOW to Write End  
SCE  
AW  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
7
0
HA  
0
SA  
7
PWE  
SD  
Data Set-Up to Write End  
Data Hold from Write End  
6
0
HD  
WE HIGH to Low Z  
3
LZWE  
HZWE  
WE LOW to High Z  
5
Notes  
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
I
t
t
/I and 30-pF load capacitance.  
OL OH  
7.  
8.  
gives the minimum amount of time that the power supply should be at typical V values until the first memory access can be performed.  
POWER  
, t  
, and t  
are specified with a load capacitance of 5 pF as in part (c) of “AC Test Loads and Waveforms ” on page 4. Transition is measured when the outputs  
HZOE HZCE  
HZWE  
enter a high impedance state.  
9. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any given device.  
HZCE  
LZCE HZOE  
LZOE  
HZWE  
LZWE  
10. This parameter is guaranteed by design and is not tested.  
11. The internal write time of the memory is defined by the overlap of CEand WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals  
can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.  
Document #: 38-05459 Rev. *E  
Page 5 of 11  
 
           
CY7C106D  
CY7C1006D  
Data Retention Characteristics (Over the Operating Range)  
Parameter  
Description  
for Data Retention  
CC  
Conditions  
Min  
Max  
Unit  
V
V
V
2.0  
DR  
I
Data Retention Current  
V
= V = 2.0V, CE > V – 0.3V,  
3
mA  
CCDR  
CC  
DR  
CC  
V
> V – 0.3V or V < 0.3V  
IN  
CC IN  
[4]  
t
t
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
ns  
ns  
CDR  
t
R
RC  
Data Retention Waveform  
DATA RETENTION MODE  
> 2V  
4.5V  
4.5V  
V
V
DR  
CC  
t
t
R
CDR  
CE  
Switching Waveforms  
Read Cycle No.1 (Address Transition Controlled)  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
Read Cycle No. 2 (OE Controlled)  
ADDRESS  
CE  
t
RC  
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA VALID  
DATA OUT  
t
LZCE  
t
PD  
ICC  
t
V
CC  
PU  
50%  
SUPPLY  
CURRENT  
50%  
ISB  
Notes  
13. Full device operation requires linear V ramp from V to V  
> 50 µs or stable at V > 50 µs.  
CC(min)  
CC  
DR  
CC(min)  
14. tr < 3 ns for all speeds.  
15. Device is continuously selected, OE and CE = V .  
IL  
16. WE is HIGH for read cycle.  
Document #: 38-05459 Rev. *E  
Page 6 of 11  
 
       
CY7C106D  
CY7C1006D  
Switching Waveforms (continued)  
Write Cycle No. 1 (CE Controlled)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA IO  
DATA VALID  
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)  
t
WC  
ADDRESS  
t
SCE  
CE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
OE  
t
t
SD  
HD  
DATA IO  
DATA VALID  
t
HZOE  
Notes  
18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.  
19. Data IO is high impedance if OE = V  
.
IH  
Document #: 38-05459 Rev. *E  
Page 7 of 11  
 
   
CY7C106D  
CY7C1006D  
Switching Waveforms (continued)  
Write Cycle No. 3 (WE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA VALID  
DATA IO  
t
t
LZWE  
HZWE  
Truth Table  
CE  
H
L
OE  
X
WE  
X
Input/Output  
High Z  
Mode  
Power  
Power-Down  
Read  
Standby (I  
)
SB  
L
H
Data Out  
Data In  
High Z  
Active (I  
Active (I  
Active (I  
)
CC  
L
X
L
Write  
)
CC  
L
H
H
Selected, Outputs Disabled  
)
CC  
Ordering Information  
Speed  
Package  
Diagram  
Operating  
Range  
Package Type  
(ns)  
Ordering Code  
CY7C106D-10VXI  
CY7C1006D-10VXI  
10  
51-85032  
51-85031  
28-pin (400-Mil) Molded SOJ (Pb-free)  
28-pin (300-Mil) Molded SOJ (Pb-free)  
Industrial  
Please contact your local Cypress sales representative for availability of these parts.  
Document #: 38-05459 Rev. *E  
Page 8 of 11  
 
CY7C106D  
CY7C1006D  
Package Diagrams  
Figure 1. 28-pin (300-Mil) Molded SOJ, 51-85031  
NOTE :  
1. JEDEC STD REF MO088  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE  
MIN.  
3. DIMENSIONS IN INCHES  
MAX.  
DETAIL  
A
PIN 1 ID  
EXTERNAL LEAD DESIGN  
14  
1
0.291  
0.300  
0.330  
0.350  
0.026  
0.032  
0.013  
0.019  
15  
28  
0.014  
0.020  
OPTION 1  
OPTION 2  
0.697  
0.713  
SEATING PLANE  
0.120  
0.140  
0.007  
0.013  
0.004  
A
0.262  
0.272  
0.050  
TYP.  
0.025 MIN.  
51-85031-*C  
Document #: 38-05459 Rev. *E  
Page 9 of 11  
 
CY7C106D  
CY7C1006D  
Package Diagrams  
Figure 2. 28-pin (400-Mil) Molded SOJ, 51-85032  
PIN 1 I.D  
1
14  
MIN.  
MAX.  
DIMENSIONS IN INCHES  
.435  
.445  
.395  
.405  
15  
28  
.720  
.730  
SEATING PLANE  
.128  
.148  
.007  
.013  
0.004  
.026  
.032  
.360  
.380  
51-85032-*B  
.025 MIN.  
.015  
.020  
All product and company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-05459 Rev. *E  
Page 10 of 11  
© Cypress Semiconductor Corporation, 2006-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for  
the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended  
to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize  
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
 
CY7C106D  
CY7C1006D  
Document History Page  
Document Title: CY7C106D/CY7C1006D, 1-Mbit (256K x 4) Static RAM  
Document Number: 38-05459  
Orig. of  
REV.  
ECN NO. Issue Date  
Description of Change  
Advance information data sheet for C9 IPP  
I ,I ,I Specs are modified as per EROS (Spec # 01-2165)  
CC SB1 SB2  
Change  
**  
201560  
233693  
See ECN  
See ECN  
SWI  
*A  
RKF  
Pb-free offering in the ‘ordering information’  
*B  
262950  
See ECN  
RKF  
Added T Spec in Switching Characteristics table  
Shaded ‘Ordering Information’  
power  
*C  
*D  
See ECN See ECN  
RKF  
VKN  
Reduced Speed bins to -10 and -12 ns  
560995  
See ECN  
Converted from Preliminary to Final  
Removed Commercial Operating range  
Removed 12 ns speed bin  
Added I values for the frequencies 83MHz, 66MHz and 40MHz  
CC  
Updated Thermal Resistance table  
Updated Ordering Information table  
Changed Overshoot spec from V +2V to V +1V in footnote #3  
CC  
CC  
*E  
802877  
See ECN  
VKN  
Changed I spec from 60 mA to 80 mA for 100MHz, 55 mA to 72 mA for  
83MHz, 45 mA to 58 mA for 66MHz, 30 mA to 37 mA for 40MHz  
CC  
Document #: 38-05459 Rev. *E  
Page 11 of 11  
 

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