Cypress Computer Hardware STK14C88 3 User Manual

STK14C88-3  
256 Kbit (32K x 8) AutoStore nvSRAM  
Features  
Functional Description  
35 ns and 45 ns access times  
The Cypress STK14C88-3 is a 256 Kb fast static RAM with  
a nonvolatile element in each memory cell. The embedded  
Automatic nonvolatile STORE on power loss  
Nonvolatile STORE under Hardware or Software control  
Automatic RECALL to SRAM on power up  
Unlimited Read/Write endurance  
Unlimited RECALL cycles  
nonvolatile  
elements  
incorporate  
QuantumTrap™  
technology producing the world’s most reliable nonvolatile  
memory. The SRAM provides unlimited read and write  
cycles, while independent, nonvolatile data resides in the  
highly reliable QuantumTrap cell. Data transfers from the  
SRAM to the nonvolatile elements (the STORE operation)  
takes place automatically at power down. On power up, data  
is restored to the SRAM (the RECALL operation) from the  
nonvolatile memory. Both the STORE and RECALL opera-  
tions are also available under software control.  
1,000,000 STORE cycles  
100 year data retention  
Single 3.3V+0.3V power supply  
Commercial and Industrial Temperatures  
32-pin (300mil) SOIC and 32-pin (600 mil) PDIP packages  
RoHS compliance  
Logic Block Diagram  
V
CC  
V
CAP  
Quantum Trap  
512 X 512  
POWER  
CONTROL  
A5  
STORE  
A6  
A7  
A8  
RECALL  
STORE/  
RECALL  
CONTROL  
STATIC RAM  
ARRAY  
512 X 512  
HSB  
A9  
A11  
A12  
A13  
A14  
SOFTWARE  
DETECT  
A13  
-A0  
DQ0  
COLUMN I/O  
DQ1  
DQ2  
DQ3  
COLUMN DEC  
DQ4  
DQ5  
A0  
A4  
A10  
A1  
A3  
A2  
DQ6  
DQ7  
OE  
CE  
WE  
Cypress Semiconductor Corporation  
Document Number: 001-50592 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 29, 2009  
 
STK14C88-3  
Figure 2. AutoStore Mode  
Device Operation  
The STK14C88-3 nvSRAM is made up of two functional compo-  
nents paired in the same physical cell. These are an SRAM  
memory cell and a nonvolatile QuantumTrap cell. The SRAM  
memory cell operates as a standard fast static RAM. Data in the  
SRAM is transferred to the nonvolatile cell (the STORE  
operation) or from the nonvolatile cell to SRAM (the RECALL  
operation). This unique architecture enables the storage and  
recall of all cells in parallel. During the STORE and RECALL  
operations, SRAM READ and WRITE operations are inhibited.  
The STK14C88-3 supports unlimited reads and writes similar to  
a typical SRAM. In addition, it provides unlimited RECALL opera-  
tions from the nonvolatile cells and up to one million STORE  
operations.  
SRAM Read  
The STK14C88-3 performs a READ cycle whenever CE and OE  
are LOW while WE and HSB are HIGH. The address specified  
on pins A0–14 determines the 32,768 data bytes accessed. When  
the READ is initiated by an address transition, the outputs are  
valid after a delay of tAA (READ cycle 1). If the READ is initiated  
by CE or OE, the outputs are valid at tACE or at tDOE, whichever  
is later (READ cycle 2). The data outputs repeatedly respond to  
address changes within the tAA access time without the need for  
transitions on any control input pins, and remains valid until  
another address change or until CE or OE is brought HIGH, or  
WE or HSB is brought LOW.  
WRITE operation has taken place since the most recent STORE  
or RECALL cycle. Software initiated STORE cycles are  
performed regardless of whether a WRITE operation has taken  
place. An optional pull-up resistor is shown connected to HSB.  
The HSB signal is monitored by the system to detect if an  
AutoStore cycle is in progress.  
SRAM Write  
If the power supply drops faster than 20 us/volt before Vcc  
reaches VSWITCH, then a 1 ohm resistor should be connected  
between VCC and the system supply to avoid momentary excess  
A WRITE cycle is performed whenever CE and WE are LOW and  
HSB is HIGH. The address inputs must be stable prior to entering  
the WRITE cycle and must remain stable until either CE or WE  
goes HIGH at the end of the cycle. The data on the common IO  
pins DQ0–7 are written into the memory if it has valid tSD, before  
the end of a WE controlled WRITE or before the end of an CE  
controlled WRITE. Keep OE HIGH during the entire WRITE cycle  
to avoid data bus contention on common IO lines. If OE is left  
LOW, internal circuitry turns off the output buffers tHZWE after WE  
goes LOW.  
of current between VCC and VCAP  
.
AutoStore Inhibit Mode  
If an automatic STORE on power loss is not required, then VCC  
is tied to ground and +3.3V is applied to VCAP (Figure 3). This is  
the AutoStore Inhibit mode, where the AutoStore function is  
disabled. If the STK14C88-3 is operated in this configuration,  
references to VCC are changed to VCAP throughout this data  
sheet. In this mode, STORE operations are triggered through  
software control. It is not permissible to change between these  
options “On the fly”.  
AutoStore® Operation  
The STK14C88-3 can be powered in one of three storage opera-  
tions:  
During normal operation, the device draws current from VCC to  
charge a capacitor connected to the VCAP pin. This stored  
charge is used by the chip to perform a single STORE operation.  
If the voltage on the VCC pin drops below VSWITCH, the part  
automatically disconnects the VCAP pin from VCC. A STORE  
operation is initiated with power provided by the VCAP capacitor.  
Figure 2 shows the proper connection of the storage capacitor  
(VCAP) for automatic store operation. A charge storage capacitor  
having a capacity of between 68 uF and 220 uF (+20%) rated at  
4.7V should be provided.  
To reduce unnecessary nonvolatile stores, AutoStore and  
Hardware Store operations are ignored, unless at least one  
Document Number: 001-50592 Rev. **  
Page 3 of 17  
 
 
STK14C88-3  
and share a single capacitor. The capacitor size is scaled by  
the number of devices connected to it. When any one of the  
STK14C88-3 detects a power loss and asserts HSB, the  
common HSB pin causes all parts to request a STORE cycle.  
(A STORE takes place in those STK14C88-3 that are written  
since the last nonvolatile cycle.)  
Figure 3. AutoStore Inhibit Mode  
During any STORE operation, regardless of how it is initiated,  
the STK14C88-3 continues to drive the HSB pin LOW,  
releasing it only when the STORE is complete. After  
completing the STORE operation, the STK14C88-3 remains  
disabled until the HSB pin returns HIGH.  
If HSB is not used, it is left unconnected.  
Hardware RECALL (Power Up)  
During power up or after any low power condition (VCC  
<
VRESET), an internal RECALL request is latched. When VCC  
once again exceeds the sense voltage of VSWITCH, a RECALL  
cycle is automatically initiated and takes tHRECALL to complete.  
If the STK14C88-3 is in a WRITE state at the end of power up  
RECALL, the SRAM data is corrupted. To help avoid this  
situation, a 10 Kohm resistor is connected either between WE  
and system VCC or between CE and system VCC  
.
Software STORE  
Data is transferred from the SRAM to the nonvolatile memory  
by a software address sequence. The STK14C88-3 software  
STORE cycle is initiated by executing sequential CE controlled  
READ cycles from six specific address locations in exact  
order. During the STORE cycle, an erase of the previous  
nonvolatile data is first performed followed by a program of the  
nonvolatile elements. When a STORE cycle is initiated, input  
and output are disabled until the cycle is completed.  
Hardware STORE (HSB) Operation  
The STK14C88-3 provides the HSB pin for controlling and  
acknowledging the STORE operations. The HSB pin is used  
to request a hardware STORE cycle. When the HSB pin is  
driven LOW, the STK14C88-3 conditionally initiates a STORE  
operation after tDELAY. An actual STORE cycle only begins if a  
WRITE to the SRAM takes place since the last STORE or  
RECALL cycle. The HSB pin also acts as an open drain driver  
that is internally driven LOW to indicate a busy condition, while  
the STORE (initiated by any means) is in progress. Pull up this  
pin with an external 10K ohm resistor to VCAP if HSB is used  
as a driver.  
Because a sequence of READs from specific addresses is  
used for STORE initiation, it is important that no other READ  
or WRITE accesses intervene in the sequence. If they  
intervene, the sequence is aborted and no STORE or RECALL  
takes place.  
To initiate the software STORE cycle, the following READ  
sequence is performed:  
SRAM READ and WRITE operations, that are in progress  
when HSB is driven LOW by any means, are given time to  
complete before the STORE operation is initiated. After HSB  
goes LOW, the STK14C88-3 continues SRAM operations for  
tDELAY. During tDELAY, multiple SRAM READ operations take  
place. If a WRITE is in progress when HSB is pulled LOW, it  
allows a time, tDELAY to complete. However, any SRAM  
WRITE cycles requested after HSB goes LOW are inhibited  
until HSB returns HIGH.  
1. Read address 0x0E38, Valid READ  
2. Read address 0x31C7, Valid READ  
3. Read address 0x03E0, Valid READ  
4. Read address 0x3C1F, Valid READ  
5. Read address 0x303F, Valid READ  
6. Read address 0x0FC0, Initiate STORE cycle  
The software sequence is clocked with CE controlled READs.  
When the sixth address in the sequence is entered, the  
STORE cycle commences and the chip is disabled. It is  
important that READ cycles and not WRITE cycles are used  
in the sequence. It is not necessary that OE is LOW for a valid  
sequence. After the tSTORE cycle time is fulfilled, the SRAM is  
again activated for READ and WRITE operation.  
The HSB pin is used to synchronize multiple STK14C88-3  
while using a single larger capacitor. To operate in this mode,  
the HSB pin is connected together to the HSB pins from the  
other STK14C88-3. An external pull up resistor to VCAP is  
required, since HSB acts as an open drain pull down. The  
V
CAP pins from the other STK14C88-3 parts are tied together  
Document Number: 001-50592 Rev. **  
Page 4 of 17  
 
 
STK14C88-3  
Software RECALL  
Low Average Active Power  
Data is transferred from the nonvolatile memory to the SRAM by  
a software address sequence. A software RECALL cycle is  
initiated with a sequence of READ operations in a manner similar  
to the software STORE initiation. To initiate the RECALL cycle,  
the following sequence of CE controlled READ operations is  
performed:  
CMOS technology provides the STK14C88-3 the benefit of  
drawing significantly less current when it is cycled at times longer  
than 50 ns. Figure 4 and Figure 5 show the relationship between  
ICC and READ or WRITE cycle time. Worst case current  
consumption is shown for both CMOS and TTL input levels  
(commercial temperature range, VCC = 3.6V, 100% duty cycle  
on chip enable). Only standby current is drawn when the chip is  
disabled. The overall average current drawn by the STK14C88-3  
depends on the following items:  
1. Read address 0x0E38, Valid READ  
2. Read address 0x31C7, Valid READ  
3. Read address 0x03E0, Valid READ  
4. Read address 0x3C1F, Valid READ  
5. Read address 0x303F, Valid READ  
6. Read address 0x0C63, Initiate RECALL cycle  
1. The duty cycle of chip enable  
2. The overall cycle rate for accesses  
3. The ratio of READs to WRITEs  
4. CMOS versus TTL input levels  
5. The operating temperature  
6. The VCC level  
Internally, RECALL is a two step procedure. First, the SRAM data  
is cleared, and then the nonvolatile information is transferred into  
the SRAM cells. After the tRECALL cycle time, the SRAM is once  
again ready for READ and WRITE operations. The RECALL  
operation does not alter the data in the nonvolatile elements. The  
nonvolatile data can be recalled an unlimited number of times.  
7. IO loading  
Figure 4. Current Versus Cycle Time (READ)  
Preventing STORE  
The STORE function can be disabled on the fly by holding HSB  
high with a driver capable of sourcing 30 mA at a VOH of at least  
2.2V, because it has to overpower the internal pull down device.  
This device drives HSB LOW for 20 μs at the onset of a STORE.  
When the STK14C88-3 is connected for AutoStore operation  
(system VCC connected to VCC and a 68 μF capacitor on VCAP  
)
and VCC crosses VSWITCH on the way down, the STK14C88-3  
attempts to pull HSB LOW. If HSB does not actually get below  
VIL, the part stops trying to pull HSB LOW and aborts the STORE  
attempt.  
Hardware Protect  
The STK14C88-3 offers hardware protection against inadvertent  
STORE operation and SRAM WRITEs during low voltage condi-  
tions. When VCAP<VSWITCH, all externally initiated STORE  
operations and SRAM WRITEs are inhibited.  
Figure 5. Current Versus Cycle Time (WRITE)  
Noise Considerations  
The STK14C88-3 is a high speed memory. It must have a high  
frequency bypass capacitor of approximately 0.1 µF connected  
between VCC and VSS, using leads and traces that are as short  
as possible. As with all high speed CMOS ICs, careful routing of  
power, ground, and signals reduce circuit noise.  
Document Number: 001-50592 Rev. **  
Page 5 of 17  
 
   
STK14C88-3  
system manufacturing test to ensure these system routines  
work consistently. Power up boot firmware routines should  
rewrite the nvSRAM into the desired state. While the  
nvSRAM is shipped in a preset state, best practice is to again  
rewrite the nvSRAM into the desired state as a safeguard  
against events that might flip the bit inadvertently (program  
bugs or incoming inspection routines).  
Best Practices  
nvSRAM products have been used effectively for over 15  
years. While ease-of-use is one of the product’s main system  
values, experience gained working with hundreds of applica-  
tions has resulted in the following suggestions as best  
practices:  
The nonvolatile cells in an nvSRAM are programmed on the  
test floor during final test and quality assurance. Incoming  
inspection routines at customer or contract manufacturer’s  
sites, sometimes, reprogram these values. Final NV patterns  
are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.  
End product’s firmware should not assume an NV array is in  
a set programmed state. Routines that check memory  
content values to determine first time system configuration  
and cold or warm boot status, should always program a  
unique NV pattern (for example, a complex 4-byte pattern of  
46 E6 49 53 hex or more random bytes) as part of the final  
The VCAP value specified in this data sheet includes a  
minimum and a maximum value size. Best practice is to meet  
this requirement and not exceed the max VCAP value  
because the higher inrush currents may reduce the reliability  
of the internal pass transistor. Customers who want to use a  
larger VCAP value to ensure there is extra store charge  
should discuss their VCAP size selection with Cypress to  
understand any impact on the VCAP voltage level at the end  
of a tRECALL period.  
Table 2. Hardware Mode Selection  
A13 – A0  
Mode  
IO  
Power  
Standby  
Active[1]  
Active  
CE  
H
WE  
X
HSB  
H
X
X
X
X
Not Selected  
Read SRAM  
Write SRAM  
Nonvolatile Store  
Output High Z  
Output Data  
Input Data  
L
L
X
L
H
L
H
H
L
[2]  
X
H
Output High Z  
ICC2  
Active[1, 3, 4, 5]  
H
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
0x0FC0  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Nonvolatile STORE  
Active[1, 3, 4, 5]  
L
H
H
0x0E38  
0x31C7  
0x03E0  
0x3C1F  
0x303F  
0x0C63  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Nonvolatile RECALL  
Notes  
1. I/O state assumes OE < V . Activation of nonvolatile cycles does not depend on state of OE.  
IL  
2. HSB STORE operation occurs only if an SRAM WRITE has been done since the last nonvolatile cycle. After the STORE (if any) completes, the part will go  
into standby mode, inhibiting all operations until HSB rises.  
3. CE and OE LOW and WE HIGH for output behavior.  
4. The six consecutive addresses must be in the order listed. WE must be high during all six consecutive CE controlled cycles to enable a nonvolatile cycle.  
5. While there are 15 addresses on the STK14C88-3, only the lower 14 are used to control software modes.  
Document Number: 001-50592 Rev. **  
Page 6 of 17  
 
         
STK14C88-3  
Voltage on DQ0-7 or HSB .......................–0.5V to Vcc + 0.5V  
Power Dissipation ......................................................... 1.0W  
DC output Current (1 output at a time, 1s duration) .... 15 mA  
Operating Range  
Maximum Ratings  
Exceeding maximum ratings may shorten the useful life of the  
device. These user guidelines are not tested.  
Storage Temperature ................................. –65°C to +150°C  
Temperature under bias.............................. –55°C to +125°C  
Supply Voltage on VCC Relative to GND ..........–0.5V to 7.0V  
Voltage on Input Relative to Vss............0.6V to VCC + 0.5V  
Range  
Commercial  
Industrial  
Ambient Temperature  
0°C to +70°C  
VCC  
3.0V to 3.6V  
3.0V to 3.6V  
-40°C to +85°C  
DC Electrical Characteristics  
Over the operating range (VCC = 3.0V to 3.6V) [6]  
Parameter  
ICC1  
Description  
Test Conditions  
Min  
Max Unit  
Average VCC Current tRC = 35 ns  
tRC = 45 ns  
Commercial  
50  
42  
mA  
mA  
Dependent on output loading and cycle rate. Values  
obtained without output loads.  
Industrial  
52  
44  
mA  
mA  
I
OUT = 0 mA.  
Average VCC Current All Inputs Do Not Care, VCC = Max  
during STORE Average current for duration tSTORE  
Average VCC Current WE > (VCC – 0.2V). All other inputs cycling.  
ICC2  
ICC3  
3
9
mA  
mA  
at tRC= 200 ns, 5V,  
25°C Typical  
Dependent on output loading and cycle rate. Values obtained without  
output loads.  
ICC4  
AverageVCAP Current All Inputs Do Not Care, VCC = Max  
2
mA  
during AutoStore  
Cycle  
Average current for duration tSTORE  
[7]  
ISB1  
Average VCC Current tRC=35ns, CE > VIH  
(Standby, Cycling TTL tRC=45ns, CE > VIH  
Input Levels)  
Commercial  
Industrial  
18  
16  
mA  
mA  
mA  
19  
17  
[7]  
ISB2  
VCC Standby Current CE > (VCC – 0.2V). All others VIN < 0.2V or > (VCC – 0.2V).  
1
(Standby, Stable  
CMOS Input Levels)  
IIX  
Input Leakage Current VCC = Max, VSS < VIN < VCC  
-1  
-1  
+1  
+1  
μA  
μA  
IOZ  
Off State Output  
Leakage Current  
VCC = Max, VSS < VIN < VCC, CE or OE > VIH or WE < VIL  
VIH  
VIL  
Input HIGH Voltage  
2.2  
VCC  
0.5  
+
V
V
Input LOW Voltage  
VSS  
0.5  
0.8  
VOH  
VOL  
VBL  
Output HIGH Voltage IOUT = –4 mA except HSB  
Output LOW Voltage IOUT = 8 mA except HSB  
2.4  
V
V
V
0.4  
0.4  
Logic ‘0’ Voltage on  
HSB output  
IOUT = 3 mA  
VCAP  
Storage Capacitor  
Between VCAP pin and Vss, 68 to 220uF +20%, 4.7V rated.  
54  
264  
uF  
Notes  
6.  
V
reference levels throughout this data sheet refer to V if that is where the power supply connection is made, or V  
if V is connected to ground.  
CC  
CC  
CAP CC  
7. CE > V will not produce standby current levels until any nonvolatile cycle in progress has timed out.  
IH  
Document Number: 001-50592 Rev. **  
Page 7 of 17  
 
   
STK14C88-3  
Data Retention and Endurance  
Parameter  
Description  
Min  
100  
Unit  
Years  
K
DATAR  
NVC  
Data Retention  
Nonvolatile STORE Operations  
1,000  
Capacitance  
In the following table, the capacitance parameters are listed.[8]  
Parameter Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
TA = 25°C, f = 1 MHz,  
CC = 0 to 3.0 V  
Max  
5
Unit  
pF  
CIN  
V
COUT  
7
pF  
Thermal Resistance  
In the following table, the thermal resistance parameters are listed.[8]  
Parameter  
Description  
Test Conditions  
32-SOIC  
32-PDIP  
Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard test methods and  
procedures for measuring thermal impedance, per  
EIA / JESD51.  
TBD  
TBD  
°C/W  
ΘJC  
Thermal Resistance  
(Junction to Case)  
TBD  
TBD  
°C/W  
Figure 6. AC Test Loads  
R1 317Ω  
3.3V  
Output  
R2  
30 pF  
351Ω  
AC Test Conditions  
Input Pulse Levels..................................................0 V to 3 V  
Input Rise and Fall Times (10% - 90%)........................ <5 ns  
Input and Output Timing Reference Levels................... 1.5 V  
Note  
8. These parameters are guaranteed by design and are not tested.  
Document Number: 001-50592 Rev. **  
Page 8 of 17  
 
 
STK14C88-3  
AC Switching Characteristics  
SRAM Read Cycle  
Parameter  
35 ns  
45 ns  
Description  
Unit  
Cypress  
Alt  
Min  
Max  
Min  
Max  
Parameter  
tACE  
tELQV  
tAVAV, ELEH  
tAVQV  
Chip Enable Access Time  
Read Cycle Time  
35  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tRC  
t
35  
45  
tAA  
tDOE  
Address Access Time  
35  
15  
45  
20  
tGLQV  
Output Enable to Data Valid  
Output Hold After Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
tOHA  
tAXQX  
5
5
5
5
tLZCE  
tHZCE  
tLZOE  
tHZOE  
tELQX  
tEHQZ  
13  
13  
35  
15  
15  
45  
tGLQX  
0
0
0
0
tGHQZ  
[8]  
tPU  
tELICCH  
tEHICCL  
[8]  
tPD  
Switching Waveforms  
Figure 7. SRAM Read Cycle 1: Address Controlled [9, 10]  
W5&  
$''5(66  
W$$  
W2+$  
'4ꢀꢁ'$7$ꢀ287ꢂ  
'$7$ꢀ9$/,'  
Figure 8. SRAM Read Cycle 2: CE and OE Controlled [9]  
W5&  
$''5(66  
&(  
W$&(  
W3'  
W+=&(  
W/=&(  
2(  
W+=2(  
W'2(  
W/=2(  
'4ꢀꢁ'$7$ꢀ287ꢂ  
'$7$ꢀ9$/,'  
$&7,9(  
W38  
67$1'%<  
,&&  
Notes  
9. WE and HSB must be HIGH during SRAM Read Cycles.  
10. I/O state assumes CE and OE < V and WE > V ; device is continuously selected.  
IL  
IH  
11. Measured ±200 mV from steady state output voltage.  
Document Number: 001-50592 Rev. **  
Page 9 of 17  
 
     
STK14C88-3  
Table 3. SRAM Write Cycle  
Parameter  
35 ns  
45 ns  
Unit  
Description  
Write Cycle Time  
Cypress  
Parameter  
Alt  
Min  
Max  
Min  
Max  
tWC  
tAVAV  
tWLWH, WLEH  
tELWH, ELEH  
tDVWH, DVEH  
tWHDX, EHDX  
tAVWH, AVEH  
tAVWL, AVEL  
tWHAX, EHAX  
tWLQZ  
tWHQX  
35  
25  
25  
12  
0
45  
30  
30  
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tPWE  
tSCE  
tSD  
tHD  
tAW  
tSA  
tHA  
tHZWE  
tLZWE  
t
Write Pulse Width  
t
Chip Enable To End of Write  
Data Setup to End of Write  
Data Hold After End of Write  
Address Setup to End of Write  
Address Setup to Start of Write  
Address Hold After End of Write  
Write Enable to Output Disable  
Output Active After End of Write  
t
t
t
25  
0
30  
0
t
t
0
0
[11,12]  
13  
15  
5
5
Switching Waveforms  
Figure 9. SRAM Write Cycle 1: WE Controlled [13, 14]  
tWC  
ADDRESS  
CE  
tHA  
tSCE  
tAW  
tSA  
tPWE  
WE  
tHD  
tSD  
DATA VALID  
DATA IN  
tHZWE  
tLZWE  
HIGH IMPEDANCE  
PREVIOUS DATA  
DATA OUT  
Figure 10. SRAM Write Cycle 2: CE Controlled [13, 14]  
tWC  
ADDRESS  
tHA  
tSCE  
tSA  
CE  
WE  
tAW  
tPWE  
tSD  
tHD  
DATA IN  
DATA VALID  
HIGH IMPEDANCE  
DATA OUT  
Notes  
12. If WE is Low when CE goes Low, the outputs remain in the high impedance state.  
13.  
CE or WE must be greater than V during address transitions.  
IH  
14. HSB must be HIGH during SRAM WRITE cycles.  
Document Number: 001-50592 Rev. **  
Page 10 of 17  
 
     
STK14C88-3  
AutoStore or Power Up RECALL  
STK14C88-3  
Parameter  
Alt  
Description  
Unit  
Min  
Max  
tHRECALL  
tRESTORE  
tHLHZ  
Power up RECALL Duration  
STORE Cycle Duration  
550  
10  
μs  
ms  
ns  
V
[16, 17]  
tSTORE  
tVSBL  
Low Voltage Trigger (VSWITCH) to HSB low  
Low Voltage Reset Level  
300  
2.4  
VRESET  
VSWITCH  
Low Voltage Trigger Level  
2.7  
1
2.95  
V
tDELAY  
tBLQZ  
Time Allowed to Complete SRAM Cycle  
μs  
Switching Waveforms  
Figure 11. AutoStore/Power Up RECALL  
WE  
Notes  
15. t  
starts from the time V rises above V  
.
SWITCH  
HRECALL  
CC  
16. CE and OE low and WE high for output behavior.  
17. HSB is asserted low for 1us when V  
drops through V  
. If an SRAM WRITE has not taken place since the last nonvolatile cycle, HSB will be released and no  
CAP  
SWITCH  
store will take place.  
Document Number: 001-50592 Rev. **  
Page 11 of 17  
 
     
STK14C88-3  
Software Controlled STORE/RECALL Cycle  
The software controlled STORE/RECALL cycle follows. [18, 19]  
35 ns  
45 ns  
Unit  
Parameter  
Alt  
Description  
Min  
35  
0
Max  
Min  
Max  
tRC  
tAVAV  
tAVEL  
tELEH  
tELAX  
STORE/RECALL Initiation Cycle Time  
Address Setup Time  
45  
0
ns  
ns  
ns  
ns  
μs  
[18, 19]  
tSA  
tCW  
Clock Pulse Width  
25  
20  
30  
20  
[18, 19]  
tHACE  
Address Hold Time  
tRECALL  
RECALL Duration  
20  
20  
Switching Waveforms  
Figure 12. CE Controlled Software STORE/RECALL Cycle [19]  
tRC  
tRC  
ADDRESS # 1  
ADDRESS # 6  
ADDRESS  
CE  
tSA  
tSCE  
tHACE  
OE  
t
STORE / tRECALL  
HIGH IMPEDANCE  
DATA VALID  
DATA VALID  
DQ (DATA)  
Notes  
18. The software sequence is clocked on the falling edge of CE without involving OE (double clocking will abort the sequence).  
19. The six consecutive addresses must be read in the order listed in the Mode Selection table. WE must be HIGH during all six consecutive cycles.  
Document Number: 001-50592 Rev. **  
Page 12 of 17  
 
   
STK14C88-3  
Hardware STORE Cycle  
STK14C88-3  
Parameter  
Alt  
Description  
Hardware STORE Pulse Width  
Unit  
Min  
Max  
tPHSB  
tHLHX  
tRECOVER, HHQX  
15  
ns  
ns  
ns  
tDHSB  
tHLBL  
t
Hardware STORE High to Inhibit Off  
Hardware STORE Low to STORE Busy  
700  
300  
Switching Waveforms  
Figure 13. Hardware STORE Cycle  
3+6%  
Note  
20. t  
is only applicable after t  
is complete.  
STORE  
DHSB  
Document Number: 001-50592 Rev. **  
Page 13 of 17  
 
 
STK14C88-3  
Part Numbering Nomenclature  
STK14C88- 3N F 45 I TR  
Packaging Option:  
TR = Tape and Reel  
Blank = Tube  
Temperature Range:  
Blank - Commercial (0 to 70°C)  
I - Industrial (-40 to 85°C)  
Speed:  
35 - 35 ns  
45 - 45 ns  
Lead Finish  
F = 100% Sn (Matte Tin)  
Package:  
N = Plastic 32-pin 300 mil SOIC  
W= Plastic 32-pin 600 mil DIP  
Ordering Information  
Speed  
Operating  
Range  
Ordering Code  
(ns)  
Package Diagram  
Package Type  
35  
STK14C88-3NF35TR  
STK14C88-3NF35  
STK14C88-3WF35  
STK14C88-3NF35ITR  
STK14C88-3NF35I  
STK14C88-3WF35I  
STK14C88-3NF45TR  
STK14C88-3NF45  
STK14C88-3WF45  
STK14C88-3NF45ITR  
STK14C88-3NF45I  
STK14C88-3WF45I  
51-85127  
51-85127  
51-85018  
51-85127  
51-85127  
51-85018  
51-85127  
51-85127  
51-85018  
51-85127  
51-85127  
51-85018  
32-pin SOIC  
Commercial  
32-pin SOIC  
32-pin PDIP  
32-pin SOIC  
32-pin SOIC  
32-pin PDIP  
32-pin SOIC  
32-pin SOIC  
32-pin PDIP  
32-pin SOIC  
32-pin SOIC  
32-pin PDIP  
Industrial  
45  
Commercial  
Industrial  
All parts are Pb-free. The above table contains Final information. Please contact your local Cypress sales representative for availability of these parts  
Document Number: 001-50592 Rev. **  
Page 14 of 17  
 
STK14C88-3  
Package Diagrams  
Figure 14. 32-Pin (300 Mil) SOIC (51-85127)  
PIN 1 ID  
16  
1
MIN.  
MAX.  
DIMENSIONS IN INCHES[MM]  
REFERENCE JEDEC MO-119  
0.292[7.416]  
0.299[7.594]  
0.405[10.287]  
0.419[10.642]  
PART #  
17  
32  
S32.3 STANDARD PKG.  
SZ32.3 LEAD FREE PKG.  
SEATING PLANE  
0.810[20.574]  
0.822[20.878]  
0.090[2.286]  
0.100[2.540]  
0.004[0.101]  
0.050[1.270]  
TYP.  
0.006[0.152]  
0.012[0.304]  
0.041[1.041]  
0.026[0.660]  
0.032[0.812]  
0.021[0.533]  
0.004[0.101]  
0.0100[0.254]  
0.014[0.355]  
0.020[0.508]  
51-85127-*A  
Document Number: 001-50592 Rev. **  
Page 15 of 17  
 
STK14C88-3  
Package Diagrams (continued)  
Figure 15. 32-Pin (600 Mil) PDIP (51-85018)  
ꢁꢄ  
-).ꢀ  
$)-%.3)/.3 ). ).#(%3  
-!8ꢀ  
ꢀꢆꢈꢃ  
ꢀꢆꢉꢃ  
ꢁꢉ  
ꢈꢅ  
ꢀꢃꢉꢃ  
ꢀꢃꢇꢆ  
3%!4).' 0,!.%  
ꢁꢀꢄꢆꢃ  
ꢁꢀꢄꢊꢃ  
ꢀꢄꢃꢃ  
ꢀꢄꢅꢆ  
ꢀꢁꢂꢃ  
ꢀꢁꢄꢃ  
ꢀꢁꢆꢆ  
ꢀꢅꢃꢃ  
ꢀꢃꢃꢇ  
ꢀꢃꢁꢅ  
ꢈ² -).ꢀ  
ꢀꢃꢁꢆ  
ꢀꢃꢄꢃ  
ꢀꢃꢂꢆ  
ꢀꢃꢄꢆ  
ꢀꢃꢇꢃ  
ꢀꢁꢁꢃ  
ꢀꢄꢅꢆ  
ꢀꢄꢉꢃ  
ꢀꢁꢅꢃ  
ꢀꢁꢄꢃ  
ꢀꢃꢁꢆ  
ꢀꢃꢅꢃ  
51-85018-*A  
Document Number: 001-50592 Rev. **  
Page 16 of 17  
 
STK14C88-3  
Document History Page  
Document Title: STK14C88-3 256 Kbit (32K x 8) AutoStore nvSRAM  
Document Number: 001-50592  
Orig. of  
Change  
Submission  
Date  
Rev.  
ECN No.  
Description of Change  
**  
2625096  
GVCH/PYRS  
12/19/08  
New data sheet  
Sales, Solutions and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at cypress.com/sales.  
Products  
PSoC  
PSoC Solutions  
General  
Clocks & Buffers  
Wireless  
Low Power/Low Voltage  
Precision Analog  
LCD Drive  
Memories  
Image Sensors  
CAN 2.0b  
USB  
© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document Number: 001-50592 Rev. **  
Revised January 29, 2009  
Page 17 of 17  
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective  
holders.  
 

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